QSpan II (2401)
Motorola Processor-to-PCI-Bus Bridge
The QSpan II is a PCI-to-Host processor bridge for the Freescale PowerQUICC (MPC860/850/821), the QUICC (MC68360), and the MC68040. It has a growing customer list of tier-one communications vendors.
The QSpan II operates at speeds up to 50 MHz on the Host processor bus, with programmable parity and burst/prefetch capability. Its 32-bit/33 MHz PCI 2.2 support is ideal for embedded processor applications.
Another key feature of the QSpan II is its integrated PCI bus arbiter. This arbiter supports up to seven external bus masters and uses a fairness algorithm to prevent deadlocks on the bus.
The QSpanï¿½ II is an industry-proven, Freescale Semiconductor processor-to-PCI System Interconnect device. The QSpan II enables board designers to bring PCI-based embedded products to market faster, for less cost, and with high performance.
Developed as part of an ongoing strategic relationship with Freescale, QSpan II is designed to gluelessly (seamlessly) bridge the PowerQUICCï¿½ (MPC860 / MPC850 / MPC821), the QUICCï¿½ (MC68360) and the M68040 processors to the PCI bus.
With additional glue logic, QSpan II can also be connected to lower-end communications controllers and processors, such as the MC68302 and MC68030.
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