Partner Product

Model 7x40  (147)
Model 7140 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters capable of bandwidths to 40 MHz and above. The Model 7140 uses the popular PMC format and supports the emerging VITA 42 XMC standard with optional switched fabric interfaces.Also available as the Model 7840 (x8 PCIe).

A/D Converter Stage



The front end accepts two full scale

analog HF or IF inputs on front panel MMCX

connectors at +4 dBm into 50 ohms with

transformer coupling into AD6645 14-bit

105 MHz A/D converters.

The digital outputs are delivered into the

Virtex-II Pro FPGA for signal processing or

for routing to other module resources.



Digital Downconverter Stage



A TI/Graychip GC4016 quad digital

downconverter accepts either four 14-bit

inputs or three 16-bit digital inputs from

the FPGA, which determines the source of

GC4016 input data. These sources include

the A/D converters, FPGA signal processing

engines, SDRAM delay memory and

data sources on the PCI bus.

Each GC4016 channel may be set for independent

tuning frequency and bandwidth.

For an A/D sample clock frequency of

100 MHz, the output bandwidth for each

channel ranges from 5 kHz up to 2.5 MHz. By

combining two or four channels, output bandwidth

of up to 5 or 10 MHz can be achieved.



Digital Upconverter Stage



A TI DAC5686 digital upconverter (DUC)

and dual D/A accepts baseband real or complex

data streams from the FPGA with signal

bandwidths up to 40 MHz.

When operating as an upconverter, it

interpolates and translates real or complex

baseband input signals to any IF center

frequency between DC and 160 MHz. It

delivers real or quadrature (I+Q) analog

outputs through two 320 MHz 16-bit D/A

converters to two front panel MMCX connectors

at +4 dBm into 50 ohms.

If translation is disabled, the DAC5686 acts

as a two channel interpolating 16-bit D/A

with output sampling rates up to 500 MHz.



Virtex-II Pro FPGA



The Xilinx XC2VP50 Virtex-II Pro FPGA

serves as a control and status engine with

data and programming interfaces to each

of the on-board resources including the A/D

converters, GC4016 digital downconverter,

digital upconverter and D/A converters.

Factory installed FPGA functions include

data multiplexing, channel selection, data

packing, gating, triggering and SDRAM

memory control.

Option -104 adds the P4 PMC connector

with 32 pairs of LVDS connections to the

Virtex-II Pro FPGA for custom I/O.

The FPGA includes two PowerPC cores

which can be used as local microcontrollers

to create complete application engines.



Clocking and Synchronization



Two independent internal timing buses

can provide either a single clock or two

different clock rates for the input and

output signals.

Each timing bus includes a clock, a sync,Two external reference clocks are accepted,

one for each timing bus and two internal

clocks may be used for each timing bus.

A front panel 26-pin LVDS Clock/Sync

connector allows multiple modules to be

synchronized. In the slave mode, it accepts

differential LVDS inputs that drive the

clock, sync and gate signals for the two

internal timing buses.

In the master mode, the LVDS bus can

drive one or both sets of timing signals

from the two internal timing buses for

synchronizing multiple modules.

Up to seven slave 7140’s, can be driven

from the LVDS bus master, supporting

synchronous sampling and sync functions

across all connected boards. Up to 80 modules

may be synchronized with a Model 9190

Clock and Sync Generator.

147
*Complete software radio transceiver solution *VITA 42.0 XMC compatible with switched fabric interfaces *Two 105 MHz 14-bit A/Ds * Input signal bandwidth: 40 MHz * Four digital downconverters *One digital upconverter * Two 500 MHz 16-bit D/As *512 MB of DDR SDRAM *Xilinx Virtex-II Pro FPGA *Up to 1.28 seconds of delay or data capture at 100 MHz *Dual timing buses for independent input and output clock rates *LVDS clock/sync bus for multi-module synchronization *32 pairs of LVDS connections to the Virtex-II Pro FPGA for custom I/O on P4 *Optional factory-installed IP Cores available *Ruggedized and conductioncooled versions available
Model 7x40
A/D Converter Stage The front end accepts two full scale analog HF or IF inputs on front panel MMCX connectors at +4 dBm into 50 ohms with transformer coupling into AD6645 14-bit 105 MHz A/D converters. The digital outputs are delivered into the Virtex-II Pro FPGA for signal processing or for routing to other module resources. Digital Downconverter Stage A TI/Graychip GC4016 quad digital downconverter accepts either four 14-bit inputs or three 16-bit digital inputs from the FPGA, which determines the source of GC4016 input data. These sources include the A/D converters, FPGA signal processing engines, SDRAM delay memory and data sources on the PCI bus. Each GC4016 channel may be set for independent tuning frequency and bandwidth. For an A/D sample clock frequency of 100 MHz, the output bandwidth for each channel ranges from 5 kHz up to 2.5 MHz. By combining two or four channels, output bandwidth of up to 5 or 10 MHz can be achieved. Digital Upconverter Stage A TI DAC5686 digital upconverter (DUC) and dual D/A accepts baseband real or complex data streams from the FPGA with signal bandwidths up to 40 MHz. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog outputs through two 320 MHz 16-bit D/A converters to two front panel MMCX connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5686 acts as a two channel interpolating 16-bit D/A with output sampling rates up to 500 MHz. Virtex-II Pro FPGA The Xilinx XC2VP50 Virtex-II Pro FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, GC4016 digital downconverter, digital upconverter and D/A converters. Factory installed FPGA functions include data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. Option -104 adds the P4 PMC connector with 32 pairs of LVDS connections to the Virtex-II Pro FPGA for custom I/O. The FPGA includes two PowerPC cores which can be used as local microcontrollers to create complete application engines. Clocking and Synchronization Two independent internal timing buses can provide either a single clock or two different clock rates for the input and output signals. Each timing bus includes a clock, a sync,Two external reference clocks are accepted, one for each timing bus and two internal clocks may be used for each timing bus. A front panel 26-pin LVDS Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVDS inputs that drive the clock, sync and gate signals for the two internal timing buses. In the master mode, the LVDS bus can drive one or both sets of timing signals from the two internal timing buses for synchronizing multiple modules. Up to seven slave 7140’s, can be driven from the LVDS bus master, supporting synchronous sampling and sync functions across all connected boards. Up to 80 modules may be synchronized with a Model 9190 Clock and Sync Generator.
N
Hardware
Model 7140 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters capable of bandwidths to 40 MHz and above. The Model 7140 uses the popular PMC format and supports the emerging VITA 42 XMC standard with optional switched fabric interfaces.Also available as the Model 7840 (x8 PCIe).