Model 71620 (147)
Model 71620 is the first member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turn-key solution as well as a platform for developing and deploying custom FPGA processing IP. It includes three A/Ds and two D/A converters and four banks of memory. The Model 71620 is compatible with the VITA 42.0 XMC format and supports PCI Express Gen. 2 as a native interface.
*Complete radar and software radio interface solution * Supports Xilinx Virtex-6 LXT and SXT FPGAs *Three 200 MHz 16-bit A/Ds *One digital upconverter *Two 800 MHz 16-bit D/As *Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM *Sample clock synchronization to an external system reference * LVPECL clock/sync bus for multimodule synchronization *PCI Express (Gen. 1 & 2) interface up to x8 wide *VITA 42.0 XMC compatible with switched fabric interfaces *LVDS connections to the Virtex-6 FPGA for custom I/O
A/D Converter Stage
The front end accepts three full scale
analog HF or IF inputs on front panel
SSMC connectors at +8 dBm into 50 ohms
with transformer coupling into three
Texas Instruments ADS5485 200 MHz,
16-bit A/D converters.
The digital outputs are delivered into
the Virtex-6 FPGA for signal processing,
data capture or for routing to other module
Digital Upconverter and D/A Stage
A TI DAC5688 DUC (digital upconverter)
and D/A accepts a baseband real or complex
data stream from the FPGA and provides
that input to the upconvert, interpolate and
dual D/A stages.
When operating as a DUC, it interpolates
and translates real or complex baseband
input signals to any IF center frequency up
to 360 MHz. It delivers real or quadrature
(I+Q) analog outputs to the dual 16-bit D/A
converter. Analog output is through a pair
of front panel SSMC connectors.
If translation is disabled, the DAC5688
acts as a dual interpolating 16-bit D/A with
output sampling rates up to 800 MHz. In
both modes the DAC5688 provides interpolation
factors of 2x, 4x and 8x.
Xilinx Virtex-6 FPGA
The Model 71620 Cobalt architecture
features a Virtex-6 FPGA. All of the board’s
data and control paths are accessible by the
FPGA, enabling factory installed functions
including data multiplexing, channel selection,
data packing, gating, triggering and
memory control. In addition to the built-in
functions, users can install their own custom
IP for data processing. Pentek
GateFlow FPGA Design Kits facilitate integration
of user-created IP with the factory
The FPGA serves as a control and status
engine with data and programming interfaces
to each of the on-board resources
including the data converters, DDR3
SDRAM or QDRII+ SRAM memory, PCIe
interface, programmable LVDS I/O and
clock, gate, and synchronization circuits.
The FPGA can be populated with a variety
of different FPGAs to match the specific requirements of the processing task.
Clocking and Synchronization
Two internal timing buses provide either
a single clock or two different clock
rates to the A/D and D/A signal paths.
Each timing bus includes a clock, sync
and a gate or trigger signal. An on-board
clock generator receives an external sample
clock from the front panel SSMC connector.
This clock can be used directly for either
the A/D or D/A sections or can be divided
by a built-in clock synthesizer circuit to provide
different A/D and D/A clocks. In an
alternate mode, the sample clock can be
sourced from an onboard programmable
voltage-controlled crystal oscillator. In this
mode, the front panel SSMC connector can
be used to provide a 10 MHz reference
clock for synchronizing the internal oscillator.
A front panel 26-pin LVPECL Clock/
Sync connector allows multiple modules to
be synchronized. In the slave mode, it accepts
LVPECL inputs that drive the clock,
sync and gate signals. In the master mode,
the LVPECL bus can drive the timing signals
for synchronizing multiple modules.
Multiple 71620s can be driven from the
LVPECL bus master, supporting synchronous
sampling and sync functions across
all connected boards.
Intelligent DMA Engine
All memory banks are supported with
DMA engines for easily moving data through
the PCIe interface. For each transfer, the
DMA engine can automatically construct
metadata packets containing channel ID, a
sample-accurate timestamp and data
length information. These actions simplify
the host processor’s job of identifying and
executing on the data.
PCI Express Interface
The Model 71620 includes an industrystandard
interface fully compliant with PCI
Express Gen. 1 & 2 bus specifications. The
x8 lane interface includes multiple DMA
controllers for efficient transfers to and
from the module.
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