Partner Product

MFCC 8442 and MFCC 8443  (57)
PowerPC-Based Multifunction Computing PMC

The MFCC is available in three versions: intelligent, user-reprogrammable I/O PMC, and computing core PMC.



The MFCC 8443 provides a PowerPC computing core together with a large front-end field programmable gate array (FPGA) designed to implement complex, application-specific I/O functions. This front-end FPGA can be reprogrammed on a case-by-case basis by users, according to their needs. CES can assist customers to develop their own FPGA. A second FPGA implements a PowerPC-to-PCI bridge (efficient communication with the host system, including a DMA with chained block transfers). An electrical adapter carries the front-panel connector and all circuitry needed to adapt FPGA signals to the electrical levels required by a specific application (for example, PCM, MIL 1553B, AFDX).



The MFCC 8442 provides a computing kernel on PMC. It is equipped with a PowerPC 750CXe at up to 600MHz and up to 256MB of SDRAM memory.



The CES backplane driver is available on PCI, VME, and CompactPCI, and allows clusters of processors (optionally linked together) to distribute tasks, synchronize processes, and exchange messages at a very high speed (using straightforward on-board DMAs). The full TCP/IP stack is implemented on top of this backplane driver.



A low-level monitor, a VxWorks board support package, and optimized drivers/libraries are available.

57
<UL> <LI>Up to six power boosters on the same VME/CompactPCI carrier</LI> <LI>User-reprogrammable front-end FPGA (up to 600KG)</LI> <LI>PowerPC 750, 750CXe, or 74xx computing core</LI> <LI>Up to 256MB of SDRAM</LI> <LI>CES-optimized PowerPC/PCI bridge with independent, chained DMA channels<BR></LI></UL>
MFCC 8442 and MFCC 8443
The MFCC is available in three versions: intelligent, user-reprogrammable I/O PMC, and computing core PMC. The MFCC 8443 provides a PowerPC computing core together with a large front-end field programmable gate array (FPGA) designed to implement complex, application-specific I/O functions. This front-end FPGA can be reprogrammed on a case-by-case basis by users, according to their needs. CES can assist customers to develop their own FPGA. A second FPGA implements a PowerPC-to-PCI bridge (efficient communication with the host system, including a DMA with chained block transfers). An electrical adapter carries the front-panel connector and all circuitry needed to adapt FPGA signals to the electrical levels required by a specific application (for example, PCM, MIL 1553B, AFDX). The MFCC 8442 provides a computing kernel on PMC. It is equipped with a PowerPC 750CXe at up to 600MHz and up to 256MB of SDRAM memory. The CES backplane driver is available on PCI, VME, and CompactPCI, and allows clusters of processors (optionally linked together) to distribute tasks, synchronize processes, and exchange messages at a very high speed (using straightforward on-board DMAs). The full TCP/IP stack is implemented on top of this backplane driver. A low-level monitor, a VxWorks board support package, and optimized drivers/libraries are available.
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hardware
PowerPC-Based Multifunction Computing PMC