Partner Product

Model 71660  (147)
Model 71660 is the latest member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The Model 71660 is compatible with the VITA 42.0 XMC format and supports PCI Express Gen. 2 as a native interface as well as support for user installed protocols

A/D Converter Stage

The front end accepts four full scale analog

HF or IF inputs on front panel SSMC

connectors at +8 dBm into 50 ohms with

transformer coupling into four Texas Instruments

ADS5485 200 MHz, 16-bit A/D

converters.

The digital outputs are delivered into

the Virtex-6 FPGA for signal processing,

data capture or for routing to other module

resources.



Xilinx Virtex-6 FPGA



The Model 71660 Cobalt architecture

features a Virtex-6 FPGA. All of the board’s

data and control paths are accessible by the

FPGA, enabling factory installed functions

including data multiplexing, channel selection,

data packing, gating, triggering and

memory control. In addition to the built-in

functions, users can install their own custom

IP for data processing. Pentek GateFlow

FPGA Design Kits facilitate integration of

user-created IP with the factory shipped

functions.

The FPGA serves as a control and status

engine with data and programming interfaces

to each of the on-board resources

including the data converters, QDRII+

SRAM or DDR3 SDRAM memory, PCIe

interface, programmable LVDS I/O, gigabit

serial interfaces, and clock, gate, and synchronization

circuits. The FPGA can be

populated with a variety of different FPGAs

to match the specific requirements of the

processing task. Supported FPGAs include:

Virtex-6 LX130T, LX240T, LX365T, SX315T,

or SX475T.



Memory Resources

The 71660 architecture supports up to

four independent memory banks which

can be configured with all QDRII+ SRAM,

DDR3 SDRAM, or as combination of two

banks of each type of memory. Each

QDRII+ SRAM bank can be up to 8 MB

deep and is an integral part of the module’s

DMA capabilities, providing FIFO memory

space for creating DMA packets.

For applications requiring deeper memory

resources, DDR3 SDRAM banks can each

be up to 512 MB deep. Built-in memory

functions include multichannel A/D data

capture, tagging and streaming.

In addition to the factory installed functions,

custom user-installed IP within the

FPGA can take advantage of the memories

for many other purposes.



Intelligent DMA Engine

All memory banks are supported with

DMA engines for easily moving data through

the PCIe interface. These powerful linkedlist

DMA engines are capable of a unique

Acquisition Gate Driven mode.

In this mode, the length of a transfer

performed by a link definition need not

be known prior to data acquisition; rather,

it is governed by the length of the acquisition

gate. This is extremely useful in applications

where an external gate drives acquisition

and the exact length of that gate is not known

or is likely to vary.

For each transfer, the DMA engine can

automatically construct metadata packets

containing channel ID, a sample-accurate

timestamp and data length information.

These actions simplify the host processor’s

job of identifying and executing on the data.

147
*Complete radar and software radio interface solution *Supports Xilinx Virtex-6 LXT and SXT FPGAs *Four 200 MHz 16-bit A/Ds *Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM *Sample clock synchronization to an external system reference *LVPECL clock/sync bus for multimodule synchronization *PCI Express (Gen. 1 & 2) interface up to x8 wide *VITA 42.0 XMC compatible with switched fabric interfaces *LVDS connections to the Virtex-6 FPGA for custom I/O
Model 71660
A/D Converter Stage The front end accepts four full scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Xilinx Virtex-6 FPGA The Model 71660 Cobalt architecture features a Virtex-6 FPGA. All of the board’s data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, QDRII+ SRAM or DDR3 SDRAM memory, PCIe interface, programmable LVDS I/O, gigabit serial interfaces, and clock, gate, and synchronization circuits. The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-6 LX130T, LX240T, LX365T, SX315T, or SX475T. Memory Resources The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the module’s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Intelligent DMA Engine All memory banks are supported with DMA engines for easily moving data through the PCIe interface. These powerful linkedlist DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing channel ID, a sample-accurate timestamp and data length information. These actions simplify the host processor’s job of identifying and executing on the data.
N
Hardware
Model 71660 is the latest member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The Model 71660 is compatible with the VITA 42.0 XMC format and supports PCI Express Gen. 2 as a native interface as well as support for user installed protocols