Partner Product

Model 6235  (147)
Model 6235 is a dual wideband digital receiver VIM-2 module. It attaches directly to VIM-compatible processor boards and includes a Virtex-II FPGA (Field Programmable Gate Array) and two 12-bit A/Ds.

Front End

The Model 6235 accepts two analog RF

inputs at +4 dBm full scale into 50 ohms on

front panel SMA connectors.

Each of the two inputs is transformer

coupled, and digitized by an AD9432 12-bit

A/D converter. The AD9432 is capable of

operating at sample rates to 105 MHz. The

A/D converter clock can be driven from

an internal crystal oscillator or from an

external sample clock supplied through a

front panel SMA connector or front panel

sync bus.

Digital Downconverter

The digitized output of each A/D feeds

the Graychip GC1012B wideband digital

downconverter, capable of 40 MHz bandwidth

at 100 MHz sampling clock. It offers

a programmable decimation range from 2

to 64 and delivers complex 16-bit I and Q

samples to the FPGA.

Synchronization

The front panel clock and sync bus allow

one 6235 to act as a master, driving the

sample clock out to a front panel cable bus

using LVDS differential signaling. Multiple

slaves can then be clocked synchronously

with the master.

Additional sync lines allow synchronization

of the local oscillator phase, frequency

switching, decimating filter phase, and

FIFO data collection on multiple 6235’s.

147
*Two identical receiver channels include A/D, digital downconverter and a shared FPGA * Two low distortion 105 MHz 12-bit A/D converters * Wideband digital downconverters with decimation range from 2 to 64 *Output bandwidths to 40 MHz for 100 MHz sampling clock *Advanced Virtex-II FPGA for signal preprocessing *Factory-installed cores available
Model 6235
Front End The Model 6235 accepts two analog RF inputs at +4 dBm full scale into 50 ohms on front panel SMA connectors. Each of the two inputs is transformer coupled, and digitized by an AD9432 12-bit A/D converter. The AD9432 is capable of operating at sample rates to 105 MHz. The A/D converter clock can be driven from an internal crystal oscillator or from an external sample clock supplied through a front panel SMA connector or front panel sync bus. Digital Downconverter The digitized output of each A/D feeds the Graychip GC1012B wideband digital downconverter, capable of 40 MHz bandwidth at 100 MHz sampling clock. It offers a programmable decimation range from 2 to 64 and delivers complex 16-bit I and Q samples to the FPGA. Synchronization The front panel clock and sync bus allow one 6235 to act as a master, driving the sample clock out to a front panel cable bus using LVDS differential signaling. Multiple slaves can then be clocked synchronously with the master. Additional sync lines allow synchronization of the local oscillator phase, frequency switching, decimating filter phase, and FIFO data collection on multiple 6235’s.
N
Model 6235 is a dual wideband digital receiver VIM-2 module. It attaches directly to VIM-compatible processor boards and includes a Virtex-II FPGA (Field Programmable Gate Array) and two 12-bit A/Ds.