Model 5x41-420 (147)
General Information Model 5341-420 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It features two A/D and two D/A converters with built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch bridges numerous interfaces and components on the board with no latency. Also available as the Model 7841-420 (x8 PCIe) version).
*Complete software radio interface solution *3U VPX form factor *GateFlow Core 420, two high-performance wideband DDCs and interpolation filter, factory-installed *Extended DDC decimation range of 2 to 1,048,576 *Extended DDC bandwidth range of 40 MHz to 76.3 Hz *Extended DUC interpolation range of 2 to 32,768 *Extended DUC bandwidth range of 40 MHz to 2.44 kHz *LVDS clock/sync bus for multiboard synchronizatio
Core 420 Wideband Downconverter
Like the GC4016, the Core 420 downconverter
translates any frequency band
within the input bandwidth range down to
zero frequency. A complex FIR low pass
filter then removes any out of band frequency
components. An output decimator and
formatter deliver output data in either real
or complex representation. An input gain
block scales both I and Q data streams by a
16-bit gain term. The NCO provides over
118 dB spurious-free dynamic range (SFDR).
The mixer utilizes four 18x18-bit multipliers
to handle the complex inputs from the
NCO and the complex data input samples.
The FIR filter is capable of storing and utilizing
up to four independent sets of 18-bit
coefficients for each decimation value.
These coefficients are user-programmable
using RAM structures within the FPGA.
Two identical Core 420 DDCs are factory
installed in the FPGA. The decimation settings
of 2, 4, 8, 16, 32, and 64 provide output bandwidths
from 40 MHz down to 1.25 MHz for
an A/D sampling rate of 100 MHz. It also
delivers better stopband rejection than the
GC4016 in combined channel modes.
A multiplexer in front of the Core 420
DDCs allows data to be sourced from either
the A/D converters or from the output of
the GC4016, extending the maximum
cascaded decimation factor to 1,048,576.
Core 420 Interpolation Filter
The interpolation filter included in the
420 Core, expands the interpolation factor
from 2 to 32,768 programmable in steps of
2, and relieves the host processor from performing
upsampling tasks. Including the
DUC, the maximum interpolation factor is
32,768 which is comparable to the maximum
decimation of the GC4016 narrowband DDC.
In addition to the Core 420, all the
standard features of the Model 5341 are
retained including D/A waveform generator
mode, all data routing and formatting, and
delay and transient capture memoryTwo independent internal timing buses
can provide either a single clock or two
different clock rates for the input and
Each timing bus includes a clock, a sync,
and a gate or trigger signal. Signals from
either Timing Bus A or B can be selected as
the timing source for the A/Ds, the downconverters,
the upconverters and the D/As.
Two external reference clocks are accepted,
one for each timing bus and two internal
clocks may be used for each timing bus.
Front panel 26-pin LVDS Clock/Sync
connectors allow multiple boards to be synchronized.
In the slave mode, they accept
differential LVDS inputs that drive the clock,
sync and gate signals for the two internal
In the master mode, the LVDS bus can
drive one or both sets of timing signals
from the two internal timing buses for
synchronizing multiple modules.
Up to seven slave 5341-420’s can be
driven from the LVDS bus master, supporting
synchronous sampling and sync functions
across all connected boards.
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