Model 5341 (147)
Model 5341 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It features two A/D and two D/A converters, and is capable of bandwidths to 50 MHz and above. The 5341 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications.
*Complete software radio interface solution for 3U VPX systems *Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora *Two 125 MHz 14-bit A/Ds *Four digital downconverters *One digital upconverter *Two 500 MHz 16-bit D/As *512 MB of DDR SDRAM *Xilinx Virtex-II Pro FPGA *Up to 1.28 seconds of delay or data capture at 100 MHz *Dual timing buses for independent input and output clock rates *LVDS clock/sync bus for multiboard synchronization *32 pairs of LVDS connections to the Virtex-II Pro FPGA for custom I/O *Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification)
A/D Converter Stage
The front end accepts two full scale analog
HF or IF inputs on front panel MMCX
connectors at +10 dBm into 50 ohms with
transformer coupling into LTC2255 14-bit
125 MHz A/Ds.
The digital outputs are delivered into the
Virtex-II Pro FPGA for signal processing or
for routing to other module resources.
Digital Downconverter Stage
The 5341 features a TI/Graychip GC4016
quad digital downconverter, accepting
either four 14-bit inputs or three 16-bit digital
inputs from the FPGA, which determines
the source of GC4016 input data. These
sources include the A/Ds, FPGA signal
processing engine, SDRAM delay memory
and data sources on the VPX backplane.
Each GC4016 channel may be set for independent
tuning frequency and bandwidth.
For an A/D sample clock frequency of
100 MHz, the output bandwidth for each
channel ranges from 5 kHz up to 2.5 MHz. By
combining channels, output bandwidth of up
to 5 or 10 MHz can be achieved.
Digital Upconverter Stage
A TI DAC5686 digital upconverter and
dual D/A is attached to the FPGA, accepting
baseband real or complex data streams with
signal bandwidths up to 40 MHz.
When operating as an upconverter, it
interpolates and translates real or complex
baseband input signals to any IF center
frequency between DC and 160 MHz. It
delivers real or quadrature (I+Q) analog
outputs through two 320 MHz 16-bit D/A
converters to two front panel MMCX connectors
at +4 dBm into 50 ohms.
If translation is disabled, the DAC5686
acts as a two channel interpolating 16-bit D/A
with output sampling rates up to 500 MHz.
Clocking and Synchronization
Two independent internal timing buses
can provide either a single clock or two
different clock rates for the corresponding
input and output signals.
Each timing bus includes a clock, sync,
and gate or trigger signal. Signals from
either Timing Bus can be selected as the timing
source for the A/Ds, downconverter, upconverter
and D/As. Two external reference
clocks or two internal clocks may be used
for each timing bus.
A front panel 26-pin LVDS Clock/Sync
connector allows multiple boards to be
synchronized. In the slave mode, each
accepts differential LVDS inputs that drive
the clock, sync and gate signals for the
two internal timing buses.
In the master mode, the LVDS bus can
drive one or both sets of timing signals
from the two internal timing buses for
synchronizing multiple boards.
Up to seven slave 5341 boards can be
driven from the LVDS bus master, supporting
synchronous sampling and sync functions
across all connected boards.
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